In many applications the necessity of increasing computation speed and optimizing the number of transistors and the occupied area makes the use of traditional integrated arithmetic logics more and more problematical.
One of such application is the implementation an operative unit usable in calculating known dynamic programming algorithms. Such algorithms, intensively used in the methods of speech and image recognition, consist of a very limited set of elementary logic and arithmetic operations which are to be repeated often and quickly in real time.
The most widely used technique in arithmetic logic design implements minimized Boolean equations, obtained by applying Karnaugh maps to the truth tables of the functions to be carried out, by suitable combinations of known elementary logic gates, such as NAND, NOR, NOT, EX-OR. Each elementary logic gate is then transformed into the equivalent transistor circuit in the desired technology, for example in integrated MOS technology. Finally, geometric dimensioning of the individual transistors of the structure to be integrated is performed.
The arithmetic-logic unit of the invention can be treated as a circuit performing the logic addition, integrated it by a suitable additional circuitry.
The adders known in the art have a structure composed of equal addition cells, whose number is equal to the dimension of the operands and whose carry propagates from the cell of lower weight to that of higher weight, crossing the various logic levels of each cell. The result will be stable at the output only at the end of the path of the carry signal.
Hence the carry signal propagation time limits computational speed, particularly when the operands have considerable dimensions and, as a consequence, the number of logic levels to be crossed is high.
This is due to the fact that in the known circuits the carry signal at a cell output generally feeds a considerable number of transistor gates of the subsequent cell.
Thus the switching time is relatively high due to the equivalent parasitic capacity that the output of the carry signal sees at the input of the subsequent cell. This capacity is proportional to the number of transistor gates at the input.
The problem deriving from the propagation time of the carry signal has been solved in Italian patent application entitled: "Sommatore veloce in tecnologia C-MOS" (Fast C-MOS adder), filed on 20 May 1987 in the name of the same Applicant (Application No. 67440 A-87, corresponding to the copending U.S. application Ser. No. 07/186,895 filed Apr. 27, 1988). This patent application describes an elementary cell performing logic addition between two operand bits with carry propagation in C-MOS technology which basically comprises:
a first EX-OR logic gate which receives said operand bits A, B;
a first inverter which receives an input carry Cin;
a second inverter which receives the output of said first EX-OR logic gate;
a first transfer gate which receives at the transfer input and
output of said first inverter, and which is controlled by the logic input and output levels of said second inverter; a second EX-OR logic gate which receives the input carry Cin and the output of said second inverter, and supplies the result S of the addition; and
a first pair of P-MOS transistors in series and a second pair of N-MOS transistors in series, said first and second pair being connected in series between two reference voltages, the bit of the first operand A being sent to the gate of a transistor of both pairs, the bit of the second operand B being sent to the gate of the other transistor of both pairs, the common node of said two pairs being connected to the output of said first transfer gate and supplying the output carry CoutN complemented.
Yet the problem relevant to computational speed remain unresolved for the portion of circuit which is to perform all the other operations in the unit, and chiefly for the circuit which generates internal control signals of selection of the operation and of the result at the output. This circuit in fact uses the carry signal at the adder output to generate control signals.
Moreover, collateral problems of load balancing on parallel circuit branches, which are connected with the two operands, arise as well as problems of physical displacement of the control circuit in the integrated structure, still with the aim of increasing computational speed.